halsey
09-29-2007, 09:10 PM
hi.
great to see Jessica Corbin and Patrick Norton. something to add...
Memtest86+ cannot detect all memory instability. A more reliable method is to fully stress test the complete memory pathways from the DIMMs to the memory controller-cpu.
Memtest86+ fails to detect borderline memory compatibility issues because it is unable to fully stress the memory pathways.
In the simplest explanation, as memory speed increases, the Valid Data Window tends to decreases. It is partly due to reduction in signaling time frame. This means that the amount of time to carry a single bit of data shrinks and become more vulnerable to uncertainties.
The reduction of bit period makes the signal transmission along the bus a bit more tenuous. For example, according to Altera Corporation, DDR2 533MHz memory has a Valid Data Window seven times smaller than typical SDR 100MHz memory. Therefore, faster memory modules are more sensitive to signal noise and voltage fluctuations because they have less safety margin.
DDR2 800 and beyond has a much larger exposure to signal uncertainties (various noise, jitters, EMI, crosstalks, unreliable powerup, intersymbol interference & etc.) when compared to the DDR3 at the same speed.
DDR3 advancement in topology, signal calibration, the under-rated RESET function and dynamic termination provide a MUCH more stable and reliable memory platform.
Memory Stability is dependent on the motherboard as well. Module makers claiming DDR3 going beyond 1600MHz is simply a matter PR as long as they don't say which motherboard is perfect compatible. Trying to catch "wind" in the news cycles.
Memory and motherboard designers and engineers knows of the stability problem with DDR2 at 800MHz and beyond. Stability is also IC dependent at 800MHz ++.
What is a better gauge of perfect memory stability?
Try running complex math with Prime95 for 48 hours twice.
Contact me for more details.
great to see Jessica Corbin and Patrick Norton. something to add...
Memtest86+ cannot detect all memory instability. A more reliable method is to fully stress test the complete memory pathways from the DIMMs to the memory controller-cpu.
Memtest86+ fails to detect borderline memory compatibility issues because it is unable to fully stress the memory pathways.
In the simplest explanation, as memory speed increases, the Valid Data Window tends to decreases. It is partly due to reduction in signaling time frame. This means that the amount of time to carry a single bit of data shrinks and become more vulnerable to uncertainties.
The reduction of bit period makes the signal transmission along the bus a bit more tenuous. For example, according to Altera Corporation, DDR2 533MHz memory has a Valid Data Window seven times smaller than typical SDR 100MHz memory. Therefore, faster memory modules are more sensitive to signal noise and voltage fluctuations because they have less safety margin.
DDR2 800 and beyond has a much larger exposure to signal uncertainties (various noise, jitters, EMI, crosstalks, unreliable powerup, intersymbol interference & etc.) when compared to the DDR3 at the same speed.
DDR3 advancement in topology, signal calibration, the under-rated RESET function and dynamic termination provide a MUCH more stable and reliable memory platform.
Memory Stability is dependent on the motherboard as well. Module makers claiming DDR3 going beyond 1600MHz is simply a matter PR as long as they don't say which motherboard is perfect compatible. Trying to catch "wind" in the news cycles.
Memory and motherboard designers and engineers knows of the stability problem with DDR2 at 800MHz and beyond. Stability is also IC dependent at 800MHz ++.
What is a better gauge of perfect memory stability?
Try running complex math with Prime95 for 48 hours twice.
Contact me for more details.